1. Technical Field of the Invention
This invention relates generally to communications and more particularly to circuits used to support short reach communications.
2. Description of Related Art
Communication systems are known to support wireline and wireless communications between various devices. Such communication systems include, for example, backplane, chip-to-chip, copper wire (e.g., trace), fiber optic communications, national and/or international cellular telephone systems, satellite, cable television, the Internet, point-to-point in-home wireless networks and radio frequency identification (RFID) systems. Each type of communication system is constructed, and hence operates, in accordance with one or more communication standards. For instance, short reach communication systems may operate in accordance with one or more standards including, but not limited to, IEEE 802.3##. Wireless communication systems may operate in accordance with one or more standards including, but not limited to, 3GPP, LTE, LTE Advanced, RFID, IEEE 802.11, Bluetooth, advanced mobile phone services (AMPS), digital AMPS, global system for mobile communications (GSM), code division multiple access (CDMA), local multi-point distribution systems (LMDS), multi-channel-multi-point distribution systems (MMDS), and/or variations thereof.
The following IEEE standards/draft standards are hereby incorporated herein by reference in their entirety and are made part of the present U.S. Utility Patent Application for all purposes:
1. IEEE Stds 802.3##™ (generically), “IEEE Standard for Information Technology—IEEE 802.3 is a working group and a collection of IEEE standards produced by the working group defining the physical layer and data link layer's media access control (MAC) of wired Ethernet. This is generally a local area network technology with some wide area network applications. Physical connections are made between nodes and/or infrastructure devices (hubs, switches, routers) by various types of copper or fiber cable. 802.3 is a technology that supports the IEEE 802.1 network architecture. 802.3 also defines LAN access method using CSMA/CD.
2. IEEE Std 802.3bj™, “IEEE Standard for Information technology—IEEE 802.3bj defines a 4-lane 100 Gb/sec backplane PHY for operation over links consistent with copper traces on “improved fire retardant (FR-4)” (as defined by IEEE P802.3ap or better materials to be defined by the Task Force) with lengths up to at least 1 m and a 4-lane 100 Gb/sec PHY for operation over links consistent with copper twin-axial cables with lengths up to at least 5 m.
3. IEEE Std 802.3ba™, “IEEE Standard for Information technology—IEEE 802.3ba defines a 40 Gbit/s and 100 Gbit/s Ethernet. 40 Gbit/s over 1 m backplane, 10 m Cu cable assembly (4×25 Gbit or 10×10 Gbit lanes) and 100 m of MMF and 100 Gbit/s up to 10 m of Cu cable assembly, 100 m of MMF or 40 km of SMF respectively.
4. IEEE Std 802.3bm™, “IEEE Standard for Information technology—IEEE Standard for Information technology—Telecommunications and information exchange between systems—Local and metropolitan area networks—Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Amendment: Physical Layer Specifications and Management Parameters for 40 Gb/s and 100 Gb/s Operation Over Fiber Optic Cables.
Currently, wireline and wireless communications occur within licensed or unlicensed frequency spectrums. For example, wireline systems, such as those using fiber optics as a transfer medium, operate in the GHz frequency spectrum (e.g., 25 GHz-100 GHz).
Channel loss at high data speeds (e.g., Gigabit/sec (Gb/sec) range, plus) may be influenced by decisions made around power and chip area costs. One area for consideration, input/output (I/O), uses high speed SERDES circuitry. A serializer/deserializer (SERDES) converts data between serial data and parallel interfaces in each direction. The term “SERDES” generically refers to interfaces used in various technologies and applications. The basic SERDES function is made up of two functional blocks: a Parallel In, Serial Out (PISO) block (aka Parallel-to-Serial converter) and a Serial In, Parallel Out (SIPO) block (aka Serial-to-Parallel converter).
The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external Phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also have a double-buffered register.
The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines and output data latches. The receive clock may have been recovered from the data by the serial clock recovery technique. However, SERDES which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side. Such serializer encoder and deserializer decoder blocks are generally defined in the Gigabit Ethernet specification.
Conventional high-speed SERDES I/O use 2-level non-return-to-zero (NRZ) signaling. As data rates increase to 25 Gb/sec and beyond, the power and area costs of these SERDES increase hyper-linearly with the rate. For example, a 25 Gb/sec NRZ SERDES consumes 3.5× the power of a 10 Gb/SEC NRZ SERDES.
Disadvantages of conventional approaches will be evident to one skilled in the art when presented in the disclosure that follows.